1. Field of Invention
This invention relates to integrated circuit packaging and, more particularly, to a substrate of the integrated circuit package (hereinafter xe2x80x9cpackage substratexe2x80x9d) that uses guard conductors that at least partially surround a conductor that is co-planar with the guard conductors, such that when the conductor receives noise sensitive signals those signals are protected against cross-talk from extraneous conductors.
2. Description of Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
Integrated circuits have evolved over the years. In part, the enhancement in semiconductor components (e.g., smaller and faster transistors) has contributed to the increased functionality and speed of integrated circuits. Modern integrated circuits have become denser in overall circuit components and employ smaller critical dimensions. Manufacturing of these modem integrated circuits has also advanced in order to maintain pace with the growing number of components involved for each integrated circuit. Fabrication processes have minimized feature sizes and thus, increased the number of die per wafer. The results provide an increase in the yield of the wafer, which lends itself to cost-efficient integrated circuits.
Following the manufacturing process, the integrated circuit may typically be secured within a protective semiconductor device package. There are various ways to secure an integrated circuit within a package. One way is to bond the integrated circuit to a leadframe and connect pads of the integrated circuits to leads of the leadframe. After packaging the integrated circuit so that leads extend from the finished package, the leads can be inserted into or surface mounted onto a printed circuit board using, for example, through-hole or surface mount techniques. Surface mount techniques include tape automated bonding.
Another way of packaging an integrated circuit is to simply flip the integrated circuit and bond the bonding pads to an array of receptors on a package substrate. In one example, a package substrate for a flip-chip application is a ball grid array (xe2x80x9cBGAxe2x80x9d) substrate. A BGA package substrate may be made of, for example, fiberglass-epoxy printed circuit board material or a ceramic material (e.g., aluminum oxide, alumina, Al2O3, or aluminum nitride, AIN), and it may be a single layer or a multi-layer fabricated substrate. The package substrate may include a layer in which a patterned conductive material forms an electrical conductor (e.g., a power conductor plane, a ground conductor plane, etc.). In some instances, the package substrate may also include routing layers directing input and output signals through the substrate. To attach the integrated circuit, the topside of the integrated circuit is thus flipped over on top of the package substrate and typically secured using a solder reflow technique. The package substrate and the flipped integrated circuit can then be encapsulated to form the overall package. In order to route the signals between the integrated circuit and the package substrate, a plurality of vias are included to provide a connection path.
As integrated circuits become more dense and complex, there is a concern with preserving signal integrity of signals routed through the substrate and the overall noise of a package. Cross-talk can occur when mutual inductance and coupling capacitance occurs between two signals routed in close proximity to each other. Cross-talk noise can cause significant signal integrity problems in system applications.
While it is sometimes unavoidable to prevent undue cross-talk between conductors that extends across an integrated circuit substrate, it is conceivable that cross-talk can be substantially eliminated within a package substrate. An integrated circuit substrate is that across which conductors of an integrated circuit are formed. Distinguishable from an integrated circuit substrate is the package substrate. A package substrate may contain multiple layers of conductors, some of which may be dedicated to power, ground, or signal conductors, but all of which are contained within the package substrate. The integrated circuit substrate generally comprises silicon crystal silicon and resident on the substrate arc multiple layers that form a wafer. The wafer is diced into separate die that are then placed, in flip chip fashion, for example, onto the package substrate. The package substrate therefore provides an interface between the integrated circuit and the printed circuit board (PCB).
When an integrated circuit is to be bonded to a package substrate, the integrated circuit can be bonded in a flip-chip arrangement, with the integrated circuit inverted and coupled to the package substrate. The trace conductors extending across the surface of the integrated circuit are generally densely packed. Yet, when those conductors of an integrated circuit are coupled to conductors within multiple layers of the package substrate, conductors within the package substrate can undergo considerable xe2x80x9cfanout.xe2x80x9d This means that the conductors within the package substrate can be spaced further from each other than the more densely packed conductors on the integrated circuit substrate. There may be numerous mechanisms in which to isolate noise within conductors on an integrated circuit; however, a conventional technique used to isolate noise among conductors of a package substrate is to simply space the conductors further from each other using the conventional fanout technique. However, fanout will not be sufficient in all circumstances, and certainly will not be adequate if one or more signals are especially sensitive to noise. In most instances, the trace conductors in the package substrate are much longer than trace conductors in the integrated circuit. While fanout provides help in spreading out the rather long signal trace conductors, the added length needed to effectuate fanout (as well as the large input/output count and body size of the package substrate) can increase the cross-talk noise within the package.
It would be desirable to introduce a packaging substrate that can more effectively reduce noise cross-talk among signals of adjacent conductors. The desired package substrate should be one that uses a more elaborate isolation mechanism than simply spacing the conductors further apart, and thus unduly consuming valuable substrate area. While noise induced in two signals of closely spaced conductors upon a die, or integrated circuit, is problematic, remedies against inducing additional noise among conductors within a package substrate must be sought. The desired improvement is thereby one that is focused on noise reduction in the package substrate, and not necessarily that of the integrated circuit substrate.
The problems outlined above may be in large part addressed by a multi-layer package substrate that dedicates guard conductors to minimize noise from being coupled onto conductors containing noise-sensitive signals, hereinafter referred to as noise-sensitive conductors. The package substrate may include a plurality of layers, in which one layer, preferably a surface of the package substrate may contain a plurality of terminals. The terminals can be used to couple with the integrated circuit on one surface of the package substrate or with a PCB on the opposite surface of the package substrate. The terminals that couple to the integrated circuit are often referred to as solder bumps, and the terminals that couple to the PCB are often referred to as solder balls. The terminals therefore provide input/output signals that are sent between the integrated circuit (or circuits) placed on one surface of the package substrate and the PCB on the opposing surface. One terminal can receive a ground voltage supply (or power supply) that is then routed to the layer containing a ground conductor (or power supply conductor).
In addition to the co-planar terminals placed on opposing surface of the package substrate, the package substrate can also include a plane spaced vertically between the opposing surfaces. The plane is dielectrically spaced (except for vias) from the surfaces on which the terminals reside, and can accommodate a plurality of co-planar trace conductors. This layer of co-planar trace conductors can be referred to as a routing layer, and the co-planar trace conductors can be referred to as routing conductors. A subset of the routing conductors can receive one end of a via, and the other end of the via can extend upward or downward, through a dielectric, to the layer containing the ground terminal, for example.
Spaced from the routing layer is a first and second ground conductor plane. The first ground conductor plane may extend in a contiguous member across the substrate. In some instances, however, the ground conductor plane may be made up of a plurality of ground conductors arranged co-planar across a substrate. The first ground conductor plane may extend dielectrically spaced and parallel to the second ground conductor plane. In some embodiments, the second ground conductor plane may exist in a layer underneath the layer comprising the first ground conductor plane. However, it is understood that second ground conductor plane may exist in a layer above the layer comprising first ground conductor plane. This configuration may allow for a ground voltage supply to be provided to the routing layer, whereby the routing layer is preferably between the first and second ground conductor planes. The routing layer may be extended across the substrate parallel to and dielectrically spaced from the first and second ground conductor planes.
In order to provide an electrical connection, a first via can be arranged perpendicular to the first ground conductor plane. The first via may extend from the first ground conductor to the second ground conductor, with a portion of a conductor within the routing layer coupled in the interim. The interim conductor can be referred to as a guard conductor, with first vias periodically tapping the guard conductor as the guard conductor extends along the routing layer. This may allow the conductor to be referenced to the same reference structure (e.g., first and/or second ground conductor planes) and thus, minimize the voltage variation on the guard conductor. The guard conductor can be used to electrically isolate one or more noise-sensitive conductors placed between pairs of guard conductors. The noise-sensitive conductors and the guard conductors are co-planar to each other, yet spaced from each other across the routing layer. The guard conductor provides electrical isolation to the noise-sensitive conductors by being dielectrically spaced and substantially parallel to the noise-sensitive conductors with no intervening conductors there between. Due to the minimized voltage variation on the ground conductor, the noise-sensitive signals may not be affected by a voltage transition of a neighboring signal, and thus the signal integrity of the noise-sensitive signals is preserved.
In some embodiments, the noise-sensitive signals within the noise-sensitive conductors are those derived from or can be feed to, e.g., clocked circuitry, voltage reference circuitry, etc. Noise-sensitive conductors may also comprise a pair of spaced conductors, such as conductors that receive differential clock signals or differential voltage pairs sent to or from the integrated circuit. Noise-sensitive conductors can also include conductors designed to carry the power supply or ground supply voltages to and from the integrated circuit. The cross-sectional width of a noise-sensitive signal may be increased. The increased width helps minimize the parasitic resistance and inductance.
It is recognized that the package substrate is altogether different from the integrated circuit substrate. The package substrate is, therefore, referred to as the integrated circuit package substrate, which includes a first layer, a second layer, and a third layer. The first layer can include a contiguous planar element that extends across the entire first layer or alternatively, only portion of the first layer is occupied; that portion being a first ground conductor. The second layer can include a second ground conductor. Preferably, the first ground conductor and the second ground conductor extend along the same axis, co-linear with one another, yet spaced from one another. The third layer includes a routing layer. The third layer is dielectrically spaced between the first and second layers. Preferably, a guard conductor, and more preferably, a pair of guard conductors are placed upon the third layer. The guard conductor, or guard conductors extend parallel to each other along a third axis that is spaced from, yet extends along the same vector direction (i.e., co-linear) with the first and second axis. A plurality of first vias that are preferably spaced equi-distant from each other extend between the first ground conductor and each of the pair of guard conductors. Likewise a plurality of second vias spaced preferably equi-distant from each other extend between the second ground conductor and each of the pair of guard conductors. The spaced plurality of first and second vias extend at regular intervals along the same axis as the guard conductors, where the first vias can be directly over the second vias or interspersed between and over pairs of second vias.
According to another configuration, the integrated circuit package substrate can simply include a pair of guard conductors partially surrounding at least one signal conductor, where the pair of guard conductors arm arranged co-planar with one another and are substantially parallel to one another within the routing layer of the substrate. The signal conductor is also placed within the routing layer parallel to each of the pair of guard conductors. Preferably the signal conductor, or multiple signal conductors, is placed between the pair of guard conductors. The guard conductors can receive a ground voltage from a plurality of equal-spaced vias extending perpendicular to the plane in which the pair of guard conductors extend.
According to yet another example, a semiconductor package is defined to be a package substrate that extends outside of, and exclusive of, an integrated circuit. The package substrate can receive the integrated circuit on one surface of the package surface and a ground voltage supply on possible another surface of the package substrate. The package substrate can include a ground conductor coupled to the ground voltage supply through at least one supply via. A set of equi-spaced vias can also be used to extend from the ground conductor plane to a pair of guard conductors partially surrounding a signal conductor within a routing layer of the substrate.